Trench IGBT with trench gates underneath contact areas of protection diodes

ABSTRACT

A trench PT IGBT (or NPT IGBT) having clamp diodes for ESD protection and prevention of shortage among gate, emitter and collector. The clamp diodes comprise multiple back-to-back Zener Diode composed of doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above said semiconductor power device. Trench gates are formed underneath the contact areas of the clamp diodes as the buffer layer for prevention of shortage.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation in part of U.S. patent application Ser. No. 12/036,248 filed on Feb. 23, 2008

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to the cell structure, device configuration and fabrication process of trench Punch-Through insulated gate bipolar transistor (PT IGBT) and trench Non Punch-Through insulated gate bipolar transistor (NPT IGBT). More particularly, this invention relates to an improved device configuration and process to manufacture PT IGBT and NPT IGBT with ESD (electrostatic discharge) protection having the characteristics of preventing emitter, gate and collector shortage issue from happening.

2. Description of the Related Art

In order to enhance the ESD protection for trench PT IGBT and NPT IGBT, many different configurations are disclosed in prior arts with G-E Clamp Diodes or G-C Clamp Diodes or with G-E and G-C Clamp Diodes for G-E and G-C protection, respectively. As shown in FIG. 1, a conventional trench PT IGBT cell of prior art with G-E Clamp Diodes for ESD protection is illustrated. The structure further comprises: a P+ substrate 100 coated with back metal 101 on its rear side as Collector; a moderately doped N epitaxial layer 102 sandwiched between a lightly doped N− epitaxial layer 103 and the P+ substrate 100; a plurality of trenches and at least a wider trench opened within N− epitaxial layer 103 and filled with polysilicon to respectively serve as trench gates 124 and at least a wider trench gate 124′ for gate connection over a layer of gate oxide 130; P base region 104 extending among said trench gates with N+ emitter regions 105 near its top surface between two adjacent trench gates 124; a doped polysilicon layer overlying a portion of the thin oxide layer 136 as ESD protection diodes comprising two back to back Zener diodes which arranged as n+/p/n+/p/n+. Through trench contacts 126 and 127, one cathode 145 of the ESD protection diode, as well as emitter region and base region, are all connected to emitter metal 132 while another cathode 145′ together with trench gate 124′ are connected to gate metal 134 through trench contacts 128 and 129. Specially, around the bottom of each trench emitter contact and trench base contact, a P+ area is formed to reduce the resistance between base region and metal plug filled in trench contacts.

Though trench contacts employed in this prior art have better connection stability and higher device density than planar contact used in other conventional art, it will still encounter another hazardous shortage issue, which happens between gate and emitter when trench contacts 127 and 128 are over etched through ESD protection diodes and thin oxide layer 136 and into P base region 104 during fabrication process, causing accordingly low yield and reliability issues, as shown in FIG. 2. Unfortunately, this shortage problem induced by over etching may also be found in cases when G-C clamp diodes are applied as well as in conventional trench NPT IGBT with protection diodes.

Accordingly, it would be desirable to provide a trench PT IGBT (or NPT IGBT) cell with improved configuration to avoid the shortage issue resulted from over etching.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide new and improved trench PT IGBT (or NPT IGBT) cell and manufacture process to prevent shortage issue discussed above from happening when trench contacts are applied.

One advantage of the present invention is that, additional trench gates are applied in lightly doped epitaxial layer right below trench contacts in ESD protection diodes. By employing this configuration, no shortage issue will happen even if over etching takes place during manufacture process.

Another advantage of the present invention is that, no additional cost is required to implement the trench gates underneath contact areas of protection diodes since the trench gates can be formed at the same step as other trench gates formed.

Another advantage of the present invention is that, the inventive structure is suitable for both PT IGBT and NPT IGBT with G-C Clamp Diodes or with G-E Clamp Diodes or with G-C and G-E Clamp Diodes.

Briefly, in a preferred embodiment, as shown in FIG. 3B, the present invention discloses a trench PT IGBT cell with G-E Clamp Diodes for G-E ESD protection. The transistor cell comprises: a first epitaxial layer moderately doped with a first semiconductor doping type (e.g., N dopant) grown onto a substrate heavily doped with a second semiconductor doping type (e.g., P dopant) coated with a back metal on its rear side; a second epitaxial layer lightly doped with the same doping type as the first epitaxial layer and grown whereon; a plurality of trenches and at least a wider trench etched within the second epitaxial layer and filled with doped poly over a gate oxide layer to form trench gates and at least a wider trench gate for gate connection; base regions formed within the top portion of the second epitaxial layer and moderately doped with the opposite doping type to epitaxial layer; emitter regions heavily doped with the same doping type as the epitaxial layer near the front surface of base region between two adjacent trench gates; a doped polysilicon layer overlying a portion of the insulating layer as ESD protection diodes comprising multiple back to back Zener diodes which composed of doping areas of a first semiconductor doping type next to doping areas of a second semiconductor doping type; trench contacts penetrating through a thick dielectric interlayer and emitter, and extending into base regions, two cathodes of ESD protection diodes, and at least a wider trench gate to electrically connect the emitter regions, the base regions and one cathode of ESD protection diodes to the emitter metal, and to electrically connect the trench gate and another cathode of ESD protection diodes to the gate metal, respectively; an area heavily doped with the same doping type as base region around each bottom of trench emitter contact and trench base contact to reduce contact resistance between base region and metal plug filled in trench contacts. Specially, additional trench gates are formed right underneath each trench contact of the ESD protection diodes as a buffer layer to avoid G-E shortage issue.

Briefly, in another preferred embodiment, as shown in FIG. 4B, the present invention discloses a trench PT IGBT cell with G-C Clamp Diodes for G-C protection. Different from configuration in FIG. 3B, here one cathode of the ESD protection diodes is connected to gate metal while another is connected to collector metal. However, despite all that, there are still inventive trench gates right underneath each trench contact of G-C protection diodes to ward off the happening of shortage issue between G-C, or G-E, or G-C-E resulted from trench contacts of ESD protection over etching to base regions.

Briefly, in another preferred embodiment, as shown in FIG. 5B, the present invention discloses a trench PT IGBT cell with both G-E and G-C Clamp Diodes for G-E and G-C ESD protection, respectively. The pluralities of Zener Diodes contain at least three cathodes to be connected to gate metal, emitter metal and collector metal, respectively. Underneath each trench contact of protection diodes, a trench gate is formed to ward off the shortage of gate and collector to emitter resulted from trench contacts of ESD protection over etching to base regions.

Briefly, in another preferred embodiment, as shown in FIG. 6B, the present invention discloses a trench NPT IGBT cell which is similar to the configuration in FIG. 3B, except that, the two epitaxial layers onto substrate are replaced by one floating zone substrate which is lightly doped with the opposite semiconductor doping type to substrate whereunder.

Briefly, in another preferred embodiment, as shown in FIG. 7, the present invention discloses a trench NPT IGBT cell which is similar to the configuration in FIG. 4B, except that, the two epitaxial layers onto substrate are replaced by one floating zone substrate which is lightly doped with the opposite semiconductor doping type to substrate whereunder.

Briefly, in another preferred embodiment, as shown in FIG. 8, the present invention discloses a trench NPT IGBT cell which is similar to the configuration in FIG. 5B, except that, the two epitaxial layers onto substrate are replaced by one floating zone substrate which is lightly doped with the opposite semiconductor doping type to substrate whereunder.

These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:

FIG. 1 shows a cross-section of a conventional trench PT IGBT structure of prior art with ESD protection.

FIG. 2 shows the shortage issue of the conventional trench PT IGBT structure when trench contacts of protection diodes are over etched.

FIG. 3A and FIG. 3B are respectively a circuit diagram and a side cross sectional view of a trench PT IGBT of a first embodiment of the present invention.

FIG. 4A and FIG. 4B are respectively a circuit diagram and a side cross sectional view of a trench PT IGBT of another embodiment of the present invention.

FIG. 5A and FIG. 5B are respectively a circuit diagram and a side cross sectional view of a trench PT IGBT of another embodiment of the present invention.

FIG. 6 is a side cross sectional view of a trench NPT IGBT of another embodiment of the present invention.

FIG. 7 is a side cross sectional view of a trench NPT IGBT of another embodiment of the present invention.

FIG. 8 is a side cross sectional view of a trench NPT IGBT of another embodiment of the present invention.

FIGS. 9A to 9G are a serial of side cross-sectional views for showing the processing steps for fabricating a trench PT IGBT shown in FIG. 3B.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Please refer to FIG. 3A to FIG. 3B for a circuit diagram and a side cross sectional view respectively of a first preferred embodiment of this invention where a trench PT IGBT device cell with gate-emitter polysilicon Zener clamp diodes for ESD protection is disclosed. The transistor cell is formed on a P+ substrate 300 coated with back metal 301 on its rear side. Onto said substrate 300, a moderately N doped epitaxial layer 302 and a lightly N doped epitaxial layer 303 is successively grown. The trench PT IGBT device further includes trenched gates 324 and at least a wider trench gate 324′ disposed in epitaxial layer 303 with gate insulation layer 330 formed over the walls of the trenches. Base region 304 which is doped with P dopant, extends between the trenched gates 324 and 324′ with N+ emitter regions 335 near the top surface of the base region between two adjacent trench gates. In order to form G-E protection diodes, a doped polysilicon layer is formed overlying a portion of the insulating layer 336 as ESD protection diodes comprising multiple back to back Zener diodes arranged as alternating n+ and p regions adjacent to each other. Above the top surface of N− epitaxial layer 303 and the doped poly functioning as protection Zener diodes, a thick oxide layer 340 is deposited as dielectric interlayer, through which a plurality of contact trenches are opened and filled with metal plugs over a Ti/TiN barrier layer to form trench contacts 326, 327, 328 and 329. Among those trench contacts, 326 and 327 are used to connect emitter regions 335, base regions 304 and a cathode of the Zener diodes together to the emitter metal 332; 328 and 329 are used to connect trench gate 324′ and another cathode of the Zener diodes together to the gate metal 334. Around each bottom of trench 326, a P+ area is implanted to reduce the contact resistance between base regions and metal plugs filled in 326. Specially, some of trench gates 324 are formed underneath contact areas 327 and 328 of the ESD diodes to serves as a buffer layer to avoid shortage issue between emitter and gate.

Please refer to FIG. 4A to FIG. 4B for a circuit diagram and a side cross sectional view respectively of another preferred embodiment of this invention where a trench PT IGBT device with gate-collector polysilicon Zener clamp diodes for ESD protection is disclosed. The Zener diodes which are formed between gate metal and collector metal further comprises a plurality of n+ regions next to p doped regions. Underneath each trench contact of protection diodes, a trench gate 424 is formed to ward off the happening of shortage issue.

Please refer to FIG. 5A to FIG. 5B for a circuit diagram and a side cross sectional view respectively of another preferred embodiment of this invention where a trench PT IGBT device with gate-collector and gate-emitter polysilicon Zener clamp diodes for ESD protection is disclosed. The Zener diodes which are formed between gate metal and collector metal, and between gate metal and emitter metal further comprise a plurality of n+ regions next to p doped regions. Underneath each trench contact of protection diodes, a trench gate 524 is formed to ward off the happening of shortage issue.

Please refer to FIG. 6 for a side cross sectional view of another preferred embodiment of this invention where a trench NPT IGBT device cell with gate-emitter polysilicon Zener clamp diodes for ESD protection is disclosed. This semiconductor power device cell is formed in an N− floating Zone 602 grown onto P+ substrate 600. Similar to that of FIG. 3B, the Zener diodes which are formed between gate metal and emitter metal further comprise a plurality of n+ regions next to p doped regions. Underneath each trench contact of protection diodes, a trench gate 624 is formed to ward off the happening of shortage issue.

Please refer to FIG. 7 for a side cross sectional view of another preferred embodiment of this invention where a trench NPT IGBT device cell with gate-collector polysilicon Zener clamp diodes for ESD protection is disclosed. This semiconductor power device cell is formed in an N− floating Zone 702 grown onto P+ substrate 700. Similar to that of FIG. 4B, the Zener diodes which are formed between gate metal and collector metal further comprise a plurality of n+ regions next to p doped regions. Underneath each trench contact of protection diodes, a trench gate 724 is formed to ward off the happening of shortage issue.

Please refer to FIG. 8 for a side cross sectional view of another preferred embodiment of this invention where a trench NPT IGBT device with gate-collector and gate-emitter polysilicon Zener clamp diodes for ESD protection is disclosed. This semiconductor power device cell is formed in an N− floating Zone 802 grown onto P+ substrate 800. Similar to that of FIG. 5B, the Zener diodes which are formed between gate metal and collector metal, and between gate metal and emitter metal further comprise a plurality of n+ regions next to p doped regions. Underneath each trench contact of protection diodes, a trench gate 824 is formed to ward off the happening of shortage issue.

In FIG. 9A, a moderately doped N epitaxial 302 is grown on the P+ substrate 300. A trench mask (not shown) is applied to open a plurality of trenches 324 a and 324 a′ in a lightly doped N−epitaxial layer 303 supported on 302 by employing dry silicon etch process. Then, a sacrificial oxide is grown and then removed to eliminate the plasma damage may introduced during trenches etching process.

After the trench mask removal, in FIG. 9B, a gate oxide layer 330 is formed on the front surface and the inner surface of gate trenches 324 a and 324 a′. Next, the trenches 324 a and 324 a′ are filled with doped polysilicon to form trench gates 324 and at least a wider trench gate 324′ for gate connection. Then, the doped polysilicon is etched back or CMP (Chemical Mechanical Polishing) to expose the portion of the gate oxide layer that extends over the surface of N− epitaxial layer. Next, a step of P base Ion Implantation is carried out to form P base 304, and followed by a diffusion step for P base drive-in.

In FIG. 9C, an undoped polysilicon layer 320 in which ESD protection diodes will be formed is deposited over entire structure and then implanted with blank Boron Ion.

In FIG. 9D, said polysilicon 320 is etched with a poly mask so that it is completely removed from the region where the PT IGBT is defined. Accordingly, the doped polysilicon layer 320 only remains in the region where the ESD protection diode will be formed.

Next, in FIG. 9E, a photo-resist masking process is used to form source mask layer. Said source mask layer defines emitter regions of the trench PT IGBT and n+ cathode regions of the Zener diode. Then, Emitter regions 335 and cathode regions 345 and 345′ are then formed by an Arsenic or Phosphorus implantation and diffusion process.

In FIG. 9F, the source mask layer is removed in a conventional manner and a layer of thick oxide 340 is deposited over the structure to act as contact oxide interlayer. Then, a contact mask is used to define contact areas. After exposed, contact trenches are formed by dry oxide and Si etched. Finally, a step of Boron Ion Implantation is implemented to form P+ 348 around the contact trench bottom for achieving ohmic contact between P-base and metal plug.

In FIG. 9G, a Ti/TiN/W layer is deposited into contact trenches and then is etched back to form trench contact 326, 327, 328 and 329. Above hole structure, a metal layer is deposited and patterned by a metal mask (not shown) to form emitter metal 332 and gate metal 334 by dry metal etching.

Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention. 

1. A trench IGBT comprising a Zener diode connected between a gate metal and a emitter metal of said trench IGBT for functioning as a gate-emitter (G-E) diode wherein said G-E diode having trench gates underneath contact areas of said G-E diode.
 2. The trench IGBT of claim 1, wherein said G-E clamp diode comprising multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above said semiconductor power device.
 3. The trench IGBT of claim 1, wherein said trench IGBT comprising a Punch-Through type IGBT and said G-E clamp diode comprising multiple back-to-back doped regions in said polysilicon layer doped with N+ dopant ions next to a P dopant ions disposed on an insulation layer above said semiconductor power device.
 4. The trench IGBT of claim 1, wherein said trench IGBT comprising a Non-Punch-Through type IGBT and said G-E clamp diode comprising multiple back-to-back doped regions in said polysilicon layer doped with N+ dopant ions next to a P dopant ions disposed on an insulation layer above said semiconductor power device.
 5. A trench IGBT comprising a Zener diode connected between a gate metal and a collector metal of said trench IGBT for functioning as a gate-collector (G-C) diode wherein said G-C diode having trench gates underneath contact areas of said G-C diode.
 6. The trench IGBT of claim 5, wherein said G-C clamp diode comprising multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above said semiconductor power device.
 7. The trench IGBT of claim 5, wherein said trench IGBT comprising a Punch-Through type IGBT and said G-C clamp diode comprising multiple back-to-back doped regions in said polysilicon layer doped with N+ dopant ions next to a P dopant ions disposed on an insulation layer above said semiconductor power device.
 8. The trench IGBT of claim 5, wherein said trench IGBT comprising a Non-Punch-Through type IGBT and said G-C clamp diode comprising multiple back-to-back doped regions in said polysilicon layer doped with N+ dopant ions next to a P dopant ions disposed on an insulation layer above said semiconductor power device.
 9. A trench IGBT comprising a Zener diode connected between a gate metal and an emitter metal of said trench IGBT for functioning as a gate-emitter (G-E) ESD protection diode wherein said G-E diode having trench gates underneath contact area of said G-E diode; and a Zener diode connected between a gate metal and a collector metal of said trench IGBT for functioning as a gate-collector (G-C) diode wherein said G-C diode having trench gates underneath contact area of said ESD diode
 10. The trench IGBT of claim 9, wherein said G-E and G-C clamp diodes comprising multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above said semiconductor power device.
 11. The trench IGBT of claim 9, wherein said trench IGBT comprising a Punch-Through type IGBT and said G-E and G-C clamp diodes comprising multiple back-to-back doped regions in said polysilicon layer doped with N+ dopant ions next to a P dopant ions disposed on an insulation layer above said semiconductor power device.
 12. The trench IGBT of claim 9, wherein said trench IGBT comprising a Non-Punch-Through type IGBT and said G-E and G-C clamp diodes comprising multiple back-to-back doped regions in said polysilicon layer doped with N+ dopant ions next to a P dopant ions disposed on an insulation layer above said semiconductor power device.
 13. A method for manufacturing a N-channel trench IGBT comprising the steps of: growing epitaxial layer upon a heavily P doped substrate, wherein said epitaxial layers is doped with N type dopant; forming a trench mask with open and closed areas on the surface of the epitaxial layer; removing semiconductor material from exposed areas of said trench mask to form a plurality of gate trenches; growing a sacrificial oxide layer onto the surface of said trenches to remove the plasma damage introduced during opening said trenches; removing said sacrificial oxide and said trench mask; forming gate oxide on the surface of said epitaxial layer and along the inner surface of said gate trenches; depositing doped base onto the gate oxide and the gate trenches; etching back or CMP the doped poly to leave portions within the gate trenches; implanting whole device with P type dopant to form P base regions and diffusing P dopant; deposing a thick layer of undoped poly onto epitaxial layer implanting whole front surface with blank Boron; applying a poly mask over the undoped poly and etching undoped poly to leave portions for ESD protection diodes; removing the poly mask and applying an N+ area mask and implanting whole front surface with Arsenic or Phosphorus ion; removing the N+ area mask and depositing a thick oxide interlayer over whole front surface; applying a contact mask and etching the oxide, the silicon and the doped poly to form trench contacts; implanting whole front surface with Boron ion; depositing successively a layer of Ti/TiN and W and etching back to leave portion within trench contacts; depositing metal layer on the front and area side of wafer; patterning the front metal into emitter metal, gate metal and collector metal by metal etching; Backside grinding said heavily P doped substrate; Coating backside meal on said heavily P doped substrate.
 14. The method of claim 13, wherein the epitaxial layer is lightly N doped epitaxial upon a moderately N doped epitaxial layer onto the P+ substrate for N-channel PT IGBT.
 15. A method for manufacturing a N-channel trench IGBT comprising the steps of: forming a trench mask with open and closed areas on the surface of a N type Floating Zone substrate; removing semiconductor material from exposed areas of said trench mask to form a plurality of gate trenches; growing a sacrificial oxide layer onto the surface of said trenches to remove the plasma damage introduced during opening said trenches; removing said sacrificial oxide and said trench mask; forming gate oxide on the surface of said epitaxial layer and along the inner surface of said gate trenches; depositing doped base onto the gate oxide and the gate trenches; etching back or CMP the doped poly to leave portions within the gate trenches; implanting whole device with P type dopant to form P base regions and diffusing P dopant; deposing a thick layer of undoped poly onto epitaxial layer implanting whole front surface with blank Boron; applying a poly mask over the undoped poly and etching undoped poly to leave portions for ESD protection diodes; removing the poly mask and applying an N+ area mask and implanting whole front surface with Arsenic or Phosphorus ion; removing the N+ area mask and depositing a thick oxide interlayer over whole front surface; applying a contact mask and etching the oxide, the silicon and the doped poly to form trench contacts; implanting whole front surface with Boron ion; depositing successively a layer of Ti/TiN and W and etching back to leave portion within trench contacts; depositing metal layer on the front and area side of wafer; patterning the front metal into emitter metal, gate metal and collector metal by metal etching. Backside grinding said Floating Zone substrate; Ion Implanting of P+ on backside of said Floating zone substrate; Coating backside meal on said Floating Zone substrate 